1. Field of the Invention
The present invention relates to a method of manufacturing a phase change memory element. More specifically, the present invention relates to a method of manufacturing a lower electrode of a phase-change memory element using a metal interconnection and a barrier metal for forming a via.
2. Description of the Related Art
As generally known in the art, a phase-change memory element signifies a memory element in which information is stored using a difference in electrical conductivity between the crystalline phase and the amorphous phase of a specific material. In the phase change memory device, a transistor element or a diode element for addressing and reading/writing operations is provided on a semiconductor substrate and a phase-change region is electrically connected to such elements. Since information is stored using a difference in conductivity in accordance with a phase-change, data are actually stored in the phase-change memory element including the phase-change region.
The operation of the phase-change memory device will be described below. Current that flows through a transistor or a diode electrically heats the phase-change region. Therefore, the structure of the phase-change material is reversibly converted into the crystalline phase and the amorphous phase so that information is stored. Relatively low current flows to the phase-change region to measure the resistance of the phase-change material and to read the stored information.
The schematic structure of the above-mentioned phase-change memory device is illustrated in FIG. 1.
That is, referring to FIG. 1, a metal nitride layer used as a lower electrode 103 is deposited on a via 101 connected to the lower electrode and desired patterning is performed on the deposited metal nitride layer.
Then, an insulating layer 105 is deposited on the patterned lower electrode 103 and a hole is formed to connect the deposited insulating layer 105 to the lower electrode 103.
Then, a phase-change material 107 such as chalcogenide and an upper electrode 109 are sequentially deposited on an insulating layer 105 where the hole is formed. Then, an insulating layer 111 is deposited on the deposited upper electrode 109 and the hole for connecting the deposited insulating layer 111 to the upper electrode 109 is formed.
Finally, a metal interconnection 113 is deposited on the insulating layer 111 where the hole is formed to complete the phase-change memory device.
However, processes of completing the phase-change memory are very complicated. In particular, the metal nitride layer must be necessarily deposited in order to deposit the lower electrode. In consideration of the rapidly developed semiconductor process, that is, damascene and dual damascene processes, in the processes, the lower electrode can be formed the same as the conventional technology using barrier metal deposited before depositing and plating metal for forming the metal inter connection and the via. Therefore, an additional thin layer depositing process for forming a lower electrode is unnecessary so that it is necessary to develop a new process.